1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a 3D (three-dimensional) semiconductor apparatus and a data transmission method thereof.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus a 3D (three-dimensional) semiconductor apparatus has been developed. The 3D semiconductor apparatus typically includes a plurality of chips that are stacked and packaged to increase the degree of integration. In the 3D semiconductor apparatus, since two or more chips are vertically stacked, a maximum degree of integration may be achieved in a same area.
Various methods may be applied to realize the 3D semiconductor apparatus. In one of the methods, a plurality of chips having a same structure are stacked and then the plurality of chips are connected with one another using wires such as metal lines so that the plurality of chips operate as one semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which through-silicon vias are formed to pass through a plurality of stacked chips so that all the chips are electrically connected with one another. In the TSV type semiconductor apparatus, because the through-silicon vias vertically pass through respective chips to electrically connect them with one another, the area of a package may be efficiently reduced when compared to a semiconductor apparatus in which respective chips are connected with one another through peripheral wiring.
A plurality of chips constituting the 3D semiconductor apparatus typically operates by being divided into a plurality of is physical ranks or logical ranks. That is to say, a configuration is made such that a rank, selected in response to a chip select command or an address, performs a data read or write operation. The plurality of ranks each shares a data input/output lines and data pads. The data input/output lines are connected with one another by through-silicon vias which pass through the plurality of chips, and communicate with an external controller through shared channels connected with shared data pads which may be disposed in a master chip.
In a typical semiconductor apparatus, since data input lines and data output lines are commonly used, read and write operations are performed with a predetermined time interval so as to avoid collision. In the case of the 3D semiconductor apparatus described above, because the physical or logical ranks may independently perform read and write operations, the read and write operations may be performed with the predetermined time interval not secured before read or write operations. Since continuous read and write operations for the same rank are performed with the predetermined time interval, no problem is caused. However, when a read or write operation is performed for a first rank immediately after a read or write operation is performed for a second rank, data collision is likely to occur. In particular, in the case where a read operation is performed for the second rank immediately after a write operation is performed for the first rank, the probability of data collision increases.